Multi-chip package with reinforced isolation

ABSTRACT

A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

FIELD

This Disclosure relates to packaged semiconductor isolation (ISO)devices, and more particularly to packaged multi-chip ISO devices.

BACKGROUND

In circuit designs for applications where high voltage (HV) is present,such as for motor control, it is generally necessary to take steps toreduce the potential risk to users of the electrical system. These stepstraditionally include insulation, grounding, and the isolation ofdangerous HV levels by establishing a dielectric separation from the HV.Techniques for passing signal information and power across a dielectricseparation in a communication channel between integrated circuit (IC)die are known. A packaged ISO device prevents the propagation of directcurrent (DC) and unwanted AC currents between its input on one die andits output on the other die, while allowing the transmission of thedesired AC signal between the die.

The ISO device accomplishes this function using an isolation barrierbetween the first and second IC die that has a high breakdown voltageand low current leakage. A high resistance path exists across theisolation barrier, but the ISO device can still transfer informationencoded in the desired AC signal across the isolation barrier from oneIC die to the other by capacitive coupling, inductive coupling(transformer isolation), or by optical coupling. In the case oftransformer isolation, a magnetic enhanced laminate transformer is knownthat comprises a coil 1 (with N1 turns) and a coil 2 (with N2 turns)with magnetic field enhancing magnetic cores comprising a top magneticcore and a bottom magnetic core that typically comprise ferrite.

Some commercially available ISO devices comprise a DC/DC converter witha 5 kV root mean square (RMS) reinforced isolation rating designed toprovide efficient, isolated power to isolated circuits that require abias supply with a well-regulated output voltages. This ISO deviceincludes a transformer and DC/DC controller that can provide 500 mW(typical) of isolated power with a high-power conversion efficiency anda low electromagnetic interference (EMI).

Where isolation is used to enable the system to function properly, butnot necessarily to serve as a barrier against electrical shock, it isconventionally called functional isolation. Where the isolation providessufficient protection against electrical shock as long as the insulationbarrier is intact, it is conventionally called basic isolation. Safetyregulations require basic isolation to be supplemented with a secondaryisolation barrier for redundancy, so that the additional barrierprovides electrical shock protection, even if the first ISO-barrierfails. This is conventionally called double isolation. To make systemscomprising ISO devices compact and to save cost, it is desirable to haveonly one level of isolation that has the required electrical strength,reliability, and shock protection conventionally provided by two levelsof basic isolation. This isolation arrangement is conventionally calledreinforced isolation.

SUMMARY

This Summary is provided to introduce a brief selection of disclosedconcepts in a simplified form that are further described below in theDetailed Description including the drawings provided. This Summary isnot intended to limit the claimed subject matter's scope.

Disclosed aspects recognize compliance with creepage rules defined byvarious industrial standards such as underwriters laboratories (UL)1577,International Electrotechnical Commission (IEC)60747, and UL60950, limitthe thermal dissipation capability of conventional reinforced ISO devicepackages (e.g., including two IC die supporting a DC/DC converter withIC die-IC die isolation) due to the absence of an exposed die pad, andthus prevents such ISO device packages from supporting high output power(e.g., >1 W) applications. The size of the ISO device package also isconventionally enlarged to meet the creepage requirements.

Disclosed aspects include a solution to the above-described problem ofconventional ISO device packages with reinforced isolation packages byadding an isolated interposer substrate, such and interposer substrateincluding as a thermally conductive dielectric layer between top andbottom metal layers that can both be copper. A disclosed ISO devicepackage includes a first IC die including a transmitter or receiver anda second IC die including a transmitter or receiver, with a laminatetransformer providing reinforced isolation coupled between thetransmitter and the receiver on the respective IC die.

Disclosed aspects include a multi-chip ISO device package includes aleadframe including leads, an interposer substrate including a topcopper layer and a bottom metal layer, with a dielectric layerin-between. A first IC die and a second IC die both include circuitryincluding a transmitter or a receiver, and first bond pads on the firstIC die and second bond pads on the second IC die are attached top sideup in the package. A laminate transformer is attached to the top copperlayer positioned lateral to the IC die. Bondwires wirebond the firstbond pads to first pads on the laminate transformer and to a first groupof the leads or the lead terminals, and bondwires wirebond the secondbond pads to second pads on the laminate transformer and to a secondgroup of the leads or the lead terminals, and a mold compound providesencapsulation for the ISO device package.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made to the accompanying drawings, which are notnecessarily drawn to scale, wherein:

FIG. 1 is a top perspective view that shows an example multi-chip ISOdevice package which includes a first IC die including circuitrycomprising a transmitter or a receiver, and a second IC die includingcircuitry comprising a transmitter or a receiver so that the packageprovides at least one communication channel, and a laminate transformerthat is mounted to an interposer substrate that has a laminatetransformer thereon that is coupled between the transmitter and thereceiver of the respective IC die which provides reinforced isolation.

FIG. 2A is a top view depiction example multi-chip ISO device packagewhich includes a laminate transformer mounted to an interposersubstrate. The bottom view of this ISO device package provided to theright of this FIG. shows the bottom metal layer on the dielectric layerof the interposer substrate.

FIG. 2B is a side cross-sectional view of the ISO device package shownin FIG. 2A taken along cut line A-A shown in FIG. 2A, where the topcopper layer is a patterned layer, that shows the first IC die on thetop copper layer having a bond pad wirebonded to a bond pad on thelaminate dielectric of the laminate transformer that is on theinterposer substrate.

FIG. 2C is a side cross-sectional view of the ISO device package shownin FIG. 2A taken along cut line B-B shown in FIG. 2A that shows thesecond IC die on a die pad having a bond pad wirebonded to a bond pad onthe laminate dielectric of the laminate transformer which is on the topcopper layer of the interposer substrate.

FIG. 2D is a top view depiction example multi-chip ISO device packagewhich includes a laminate transformer mounted onto an interposersubstrate. In this arrangement, the top copper layer is a patternedlayer, and the interposer substrate occupies essentially the whole areaof the package so that the laminate transformer as well as the first ICdie and second IC die are all on an area of the top copper layer of theinterposer substrate.

FIG. 2E is a top view depiction example multi-chip ISO device packagewhich includes a laminate transformer mounted onto an interposersubstrate. In this arrangement, the interposer substrate takes up onlyenough area of the package so that the laminate transformer is thereon,and there are separate die pads of a leadframe for the first IC die andfor the second IC die.

FIG. 3 is a flow chart that shows steps in an example method for formingmulti-chip ISO device package that includes a laminate transformer thatis mounted onto an interposer substrate, according to an example aspect.

DETAILED DESCRIPTION

Example aspects are described with reference to the drawings, whereinlike reference numerals are used to designate similar or equivalentelements. Illustrated ordering of acts or events should not beconsidered as limiting, as some acts or events may occur in differentorder and/or concurrently with other acts or events. Furthermore, someillustrated acts or events may not be required to implement amethodology in accordance with this Disclosure.

Also, the terms “coupled to” or “couples with” (and the like) as usedherein without further qualification are intended to describe either anindirect or direct electrical connection. Thus, if a first device“couples” to a second device, that connection can be through a directelectrical connection where there are only parasitics in the pathway, orthrough an indirect electrical connection via intervening itemsincluding other devices and connections. For indirect coupling, theintervening item generally does not modify the information of a signalbut may adjust its current level, voltage level, and/or power level.

Disclosed aspects recognize the use of an interposer substrate, such asa direct bonded copper (DBC) substrate with a ceramic core dielectriclayer having reasonably good thermal conductivity such as alumina oraluminum nitride, helps performance of the multi-chip ISO device packagein at least 2 ways. The ceramic core material provides electricalisolation between the HV and low voltage nodes of the ISO device packagewithin and external to the package. The generally thick top copper layerof the interposer substrate combined with the relatively high thermalconductivity of the ceramic material that the dielectric layer of theinterposer substrate generally comprises help with enhanced heatdissipation which enables a higher power multi-chip ISO device packagesolution. Known multi-chip ISO device package solutions, such as theexposed die attach pad (DAP) small outline integrated circuit (SOIC)package, are non-isolated and generally also violate creepagerequirements.

Disclosed ISO devices generally provide the smallest area package withan exposed thermal pad which meets reinforced isolation requirements.The bottom thick copper layer of the interposer substrate provides theenhanced thermal transfer capability. The bottom copper layer alsoenables the attachment of a heat sink which will be isolated from thefirst IC die and second IC die components inside the package due to thedielectric nature of the core ceramic material.

FIG. 1 is a top perspective view that shows an example multi-chip ISOdevice package 100 which includes a first IC die 110 including circuitrycomprising a transmitter or a receiver, and a second IC die 120including circuitry comprising a transmitter or a receiver so that thepackage provides at least one communication channel. The ISO devicepackage 100 also comprises a laminate transformer 130 that is mounted toan interposer substrate 122 (e.g., a DBC substrate, such as for itsdielectric layer 122 b including ceramic such as Alumina (Al₂O₃),Aluminum Nitride (AlN), or silicon nitride) including a top copper layer122 a and a bottom metal layer 122 c with the dielectric layer 122 bbetween these metal layers.

A laminate transformer 130 is on the top copper layer 122 a, where thetransformer 130 is coupled between the transmitter and the receiver ofthe respective IC die 110, 120 which provides reinforced isolation. Thelaminate transformer 130 generally supports a root mean square (RMS)breakdown voltage of at least 1 kV for a test time of one minute,typically providing a breakdown voltage of at least 2.5 kV to 5 kV.UCC12050 has a breakdown test for a minute pursuant to UL1577 which isone of the most popular standards for isolation devices.

The interposer substrate can comprise substrates besides DBC substrates,such as for example an insulated metal substrate (IMS) which can also beused as the interposer. An IMS as known in the art comprises of a metalbaseplate (aluminum is commonly used because of its low cost anddensity) covered by a thin layer of dielectric (usually an epoxy-basedlayer, typically FR-4) and a top layer of copper (generally about 35 μmto more than 200 μm thick). The FR-4-based dielectric is usuallyprovided thin (about 100 μm thick) because it has lower thermalconductivity as compared to the ceramics used in DBC substrates. Asanother alternate, the interposer substrate can also include an activemetal brazed substrates (AMB), where a metal foil is soldered to aceramic using a solder paste. AMB is generally a higher cost arrangementcompared to DBC, but technically, AMB has essentially the sameconfiguration as DBC.

The laminate transformer 130 generally during ISO device packageoperation being the hottest component in the ISO device package beingattached to the top copper layer 122 a of the interposer substrate 122enables the heat generated by the laminate transformer 130 to bevertically conducted away. The heat transfer path for the ISO devicepackage 100 is first through the top copper layer 122 a, then throughthe dielectric layer 122 b, and then finally out the bottom metal layer122 c to the ambient which functions as a heatsink for the ISO devicepackage 100.

As noted above the dielectric layer 122 b can comprise a ceramic layer,which can provide a thermal conductivity at 20° C. of at least 20 W/m·K.For example, alumina has a Thermal Conductivity at 20° C. of 28 to 35W/m·K, aluminum nitride has a Thermal Conductivity at 20° C. of about 70to 180 W/m·K, and silicon nitride has Thermal Conductivity of about 30W/m·K at 20° C.

The interposer substrate 122 is shown by example for the ISO devicepackage 100 in FIG. 1 being L-shaped to accommodate the laminatetransformer 130 and the second IC die 120. In this example, the first ICdie 110 is lateral to the area of interposer substrate 122, and isinstead on a die pad 112 of the leadframe that is lateral to the area ofthe interposer substrate 122.

The interposer substrate 122 can also in some disclosed arrangementsoccupy essentially the whole area of the ISO device package so that thelaminate transformer 130 and the first and second IC die 110, 120 areall on a patterned top copper layer 122 a portion of the interposersubstrate 122. This arrangement is shown in FIG. 2D described below. Inanother arrangement, the interposer substrate 122 takes up only enougharea of the package so that the laminate transformer 130 is thereon, andthere are separate die pads of a leadframe for the first IC die 110 andfor the second IC die 120. This other arrangement is shown in FIG. 2Edescribed below.

The bottom metal layer 122 c can comprise copper or aluminum. The firstIC die 110 which includes circuitry 180 a and bond pads 181 a is shownon the die pad 112, while the second IC die 120 including circuitry 180b and bond pads 181 b is shown on the top copper layer 122 a of theinterposer substrate 122. The circuitry 180 a, 180 b on the IC die 110,120 as known in the art comprises circuit elements (includingtransistors, and generally diodes, resistors, capacitors, etc.) formedin the semiconductor substrate, such as in an epitaxial layer on thebulk substrate material, configured together for generally realizingeach at least a transmitter or receiver, with at least one of the IC dieproviding at least one additional circuit function. Example additionalcircuit functions include analog (e.g., amplifier, or a powerconverter), radio frequency (RF), digital, or non-volatile memoryfunctions.

The top copper layer 122 a is etched or otherwise patterned to allowelectrically isolating the second IC die 120 from the laminatetransformer 130. In the case that the first and second IC die 110, 120are both on the laminate transformer 130, which is not shown in FIG. 1,the top copper layer 122 a is patterned to isolate the first and secondIC die 110, 120 from one another, and to provide isolation from thelaminate transformer 130.

Leads are shown as 124 on one side of the ISO device package 100, andleads 114 are shown on the other side of the ISO device package 100opposite to the leads 124. There are bondwires shown as 141 between someof the leads 124 and some of the bond pads 181 a on the first IC die110, and bondwires 142 between some of the bond pads 181 a on the firstIC die 110 and some of the bond pads 130 g on the laminate dielectric130 b of the laminate transformer 130. As known in the art, what isshown as a laminate dielectric 130 b generally comprises a laminatesubstrate that has multiple metal layers (levels) with via connectionsthrough a dielectric material between the respective metal layers tobring all signals to a topmost surface of the laminate substrate.Accordingly, the bondwires 142, 143 between the IC die 110, 120 and thelaminate transformer 130 will generally make connections to the topmostcopper layer of the laminate substrate that are connected to either thetop core (shown as coil 2) or bottom core (shown as coil 1) of thelaminate transformer 130.

There are thus bondwires 143 between some of the bond pads 130 g on thelaminate transformer 130 and some of the bond pads 181 b on the secondIC die 120, and some bondwires 144 between some of the bond pads 181 bon the second IC die 120 and some of the leads 114. There are alsobondwires 145 between some of the bond pads 130 g on the laminatetransformer 130 and some of the leads 114. A mold compound 160 is alsoshown.

Although the interposer substrate 122 is shown in FIG. 1 spanning anarea of the ISO device package 100 sufficient to accommodate thelaminate transformer 130 and one of the IC die shown as the second ICdie 120, this need not be the case, such as in the case that theleadframe includes a first die pad and a second die pad for mounting thefirst IC die 110 and the second IC die 120. The top copper layer 122 aof the interposer substrate 122 thus can have thereon either one of thetwo IC die and the laminate transformer 130, both of the IC die 110, 120and the laminate transformer 130, or only the laminate transformer 130.In this case the top copper layer 122 a is patterned, the IC die 110,120 can both be mounted on the dielectric layer 122 b of the interposersubstrate 122, or one or both IC die 110, 120 can have a separate areaof the top copper layer 122 a on the dielectric layer 122 b to providedevice isolation.

It is noted that in the case that the interposer substrate 122 comprisesa DBC substrate, because a DBC substrate is typically more expensivethan a leadframe arrangement, it is generally better to keep the area ofthe DBC substrate as small if possible. An advantage of a larger areaDBC substrate with all components thereon (laminate transformer 130, thefirst IC die 110, and the second IC die 120) is a thermal benefit.Having a large area top copper layer 122 a helps the heat spreading byutilizing a larger area. Accordingly, for the ISO device package 100there is a trade-off between cost and thermal performance.

Although the multi-chip ISO device package 100 shown in FIG. 1 includesonly 2 IC die, 110, 120, disclosed multi-chip ISO device packages canhave more than 2 IC die when desired. For example, 3 IC die can beincluded instead of only 2 IC die in one disclosed multi-chip ISO devicepackage. Accordingly, disclosed multi-chip ISO device packages providescalability depending on the end application.

Disclosed multichip IC device packages can generally be used for anypower electronics circuit topology, not just for DC-DC converters.Examples beyond DC-DC converters can include a digital isolator,isolated flyback controller, isolated analog to digital converter (ADC),isolated gate driver, and isolated amplifiers.

FIG. 2A is a top view depiction example multi-chip ISO device package200 which includes a laminate transformer 130 mounted to an interposersubstrate 122, and first and second IC die 110, 120. The laminatetransformer 130 generally comprises coil 1 (with N1 turns) and coil 2(with N2 turns) each with magnetic field enhancing magnetic corescomprising a top magnetic core 130 a and a bottom magnetic core 130 c(that both typically comprise ferrite) which are spaced apart from oneanother by a laminate dielectric shown as 130 b. The bottom view of thisISO device package 200 provided to the right of this FIG. shows thebottom metal layer 122 c on the dielectric layer 122 b of the interposersubstrate 122. In this arrangement, analogous to FIG. 1 where only oneof the IC die shown as the second IC die 120 and the laminatetransformer 130 are on the interposer substrate 122, the interposersubstrate 122 again has an area large enough to accommodate the laminatetransformer 130 as well is one of the IC die now shown as the first ICdie 110, while the second IC die 120 is shown lateral to the area of theinterposer substrate 122 instead being on a die pad 112 of theleadframe.

FIG. 2B is a side cross-sectional view of the ISO device package 200shown in FIG. 2A taken along the cut line A-A shown in FIG. 2A, wherethe top copper layer 122 a is a patterned layer. FIG. 2B shows the firstIC die 110 on a portion of the top copper layer 122 a of the interposersubstrate, having a bond pad 181 a wirebonded by a bondwire 142 to abond pad 130 g of the laminate dielectric 130 b of the laminatetransformer 130 that is also on another portion of the top copper layer122 a. A mold compound 160 is shown, where the bottom metal layer 122 cof the interposer substrate 122 is shown exposed from the ISO devicepackage 200 to provide enhanced cooling for the laminate transformer130.

FIG. 2C is a side cross-sectional view of the ISO device package 200shown in FIG. 2A taken along cut line B-B shown in FIG. 2A that showsthe second IC die 120 on the die pad 112. The second IC die 120 has abond pad 181 b wirebonded to a bond pad 130 g on the laminate dielectric130 b of the laminate transformer 130, where the laminate transformer130 is on the top copper layer 122 a of the interposer substrate 122.The second IC die 120 can be seen to be lateral to the interposersubstrate 122, being instead on a die pad 112 of the leadframe.

The bottom metal layer 122 c of the interposer substrate 122 can againas in FIG. 2B be seen to be exposed from a bottom side of the ISO devicepackage 200. Disclosed arrangements have freedom to select the coolingside of the ISO device package. For example, if the end applicationneeds a topside cooling package, the backside of interposer substrate,such as copper for a DBC substrate, can also be exposed on topside ofthe ISO device package for topside heat sink attachment by flipping theview of the ISO device package 200 shown in FIG. 2C.

FIG. 2D is a top view depiction example multi-chip ISO device package240 which includes a laminate transformer 130 mounted to an interposersubstrate shown as 1221. In this arrangement, the interposer substrate1221 occupies essentially the whole area of the ISO device package 240so that the laminate transformer 130 as well as the first IC die 110 andthe second IC 120 are all on separate (patterned) areas of the topcopper layer 122 a of the interposer substrate 1221.

FIG. 2E is a top view depiction example multi-chip ISO device package260 which includes a laminate transformer 130 mounted onto an interposersubstrate shown as 122 s. In this arrangement, the interposer substrate122 s takes up only enough area of the ISO device package 260 so thatthe laminate transformer 130 is thereon, and the leadframe providesseparate die pads for the respective IC die, with a die pad 112 aprovided for the first IC die 110 and another die pad 112 b provided forthe second IC die 120.

FIG. 3 is a flow chart that shows steps in an example method 300 forforming multi-chip ISO device package that includes a laminatetransformer mounted onto an isolating interposer substrate, according toan example aspect. Step 301 shown as “raw material preparation”comprises providing a first IC die 110, a second IC die 120, a laminatetransformer 130, an interposer substrate 122, and a leadframe includingleads or lead terminals (leads 114, 124 shown in FIG. 1) that optionallyincludes one or more die pad(s). Depending on the package design, asdescribed above, the leadframe can include 0, 1, or 2 die pads, wherethe IC die can be either on die pads, or directly on the top copperlayer of the interposer substrate where the top copper layer isoptionally a patterned layer. In the case the leadframe provides no diepads (only leads or lead terminals), the interposer substrate can havean area sufficient to accommodate all the components of the ISO devicepackage, such as shown in FIG. 2D described above.

Step 302 comprises mounting the leadframe (generally a leadframepanel/array) onto a fixture, and then picking and placing an interposersubstrate inside the leads or lead terminals of the leadframe onto thefixture. The fixture can provide an accurate alignment between theleadframe and interposer substrate to enable placing the interposersubstrate within an opening in the leadframe, and a tie-bar on theleadframe can be used to physically connect interposer substrates to theleadframe panel/array. This physical connection can be accomplished byusing either an adhesive material along with reflow step, or usingmechanical clamping. Step 303 comprises dispensing an adhesive on thetop copper layer of the interposer substrate and optionally on one ormore die pads. As noted above, the adhesive generally has a thermalconductivity of at least 2 W/m·K @ 20° C., such as least 20 W/m·K @ 20°C.

Step 304 comprises picking and placing the laminate transformer on theadhesive on the top copper layer of the interposer substrate, and thefirst IC die and second IC die on the adhesive on the top copper layerof the interposer substrate when the top copper layer is a patternedlayer, or on the die pad(s) when the leadframe includes die pad(s). Step305 comprises a curing or reflow process to cure the adhesive, such ascuring at a temperature about 200° C. for about a minute. Step 306comprises wirebonding. Step 307 comprises a molding process to form amold compound, and step 308 comprises package trim and forming,including cutting the tie-bars of the leadframe.

Disclosed aspects can be integrated into a variety of assembly flows toform a variety of different multi-chip ISO packages and relatedproducts. The assembly can comprise configurations comprising aplurality of stacked semiconductor die. A variety of package substratesmay be used. The semiconductor die may include various elements thereinand/or layers thereon, including barrier layers, dielectric layers,device structures, active elements and passive elements including sourceregions, drain regions, bit lines, bases, emitters, collectors,conductive lines, conductive vias, etc. Moreover, the semiconductor diecan be formed from a variety of processes including bipolar,insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

Those skilled in the art to which this Disclosure relates willappreciate that many variations of disclosed aspects are possible withinthe scope of the claimed invention, and further additions, deletions,substitutions and modifications may be made to the above-describedaspects without departing from the scope of this Disclosure.

1-20. (canceled)
 21. A multi-chip isolation (ISO) device package,comprising: an interposer substrate comprising a top copper layer and abottom metal layer, with a dielectric layer positioned between the topcopper layer and the bottom metal layer; a laminate transformer attachedto the top copper layer positioned lateral to a first IC die and asecond IC die; bondwires wirebonding respective ones of first bond padsof the first IC die to first pads on the laminate transformer and to afirst group of leads or lead terminals; bondwires wirebonding respectiveones of second bond pads of a second IC die to second pads on thelaminate transformer and to a second group of leads or lead terminals;and a mold compound providing encapsulation for the ISO device package,wherein the bottom metal layer is exposed from the ISO device package atleast under the laminate transformer.
 22. The multi-chip package ofclaim 21, wherein the interposer substrate comprises a direct bondedcopper (DBC) substrate so that the bottom metal layer comprises copper.23. The multi-chip package of claim 21, wherein the circuitry for thefirst IC die or for the second IC die further comprises a DC/DCconverter.
 24. The multi-chip package of claim 21, wherein the laminatetransformer supports a root mean square (RMS) breakdown voltage of atleast 1 kV.
 25. The multi-chip package of claim 21, wherein the topcopper layer comprises a patterned layer.
 26. The multi-chip package ofclaim 21, wherein the dielectric layer comprises a ceramic layer whichprovides a thermal conductivity at 20° C. of at least 20 W/m·K.
 27. Themulti-chip package of claim 21, wherein the bottom metal layer isexposed from a bottom side or a topside of the ISO device package. 28.The multi-chip package of claim 21, wherein the interposer substrate isnot part of a leadframe.
 29. The multi-chip package of claim 1, whereinthe dielectric layer is not patterned.
 30. A method for forming amulti-chip isolation (ISO) device package, comprising: providing alaminate transformer; wirebonding respective ones of first bond pads ofa first IC die to first pads on the laminate transformer and to a firstgroup of leads or lead terminals, and respective ones of second bondpads of a second IC die to second pads on the laminate transformer andto a second group of leads or lead terminals, and covering the laminatetransformer, the first IC die and the second IC die and at least aportion of the first group of leads or lead terminals and at least aportion of the second group of leads or lead terminals with moldmaterial, wherein the bottom metal layer is exposed from the ISO devicepackage at least under the laminate transformer.
 31. The method of claim30, further including placing an interposer substrate comprising a topcopper layer and a bottom metal layer with a dielectric layer positionedbetween the top copper layer and the bottom metal layer, between thefirst IC die, the second IC die, the laminate transformer and the firstgroup of leads or lead terminals and the second group of leads or leadterminals.
 32. The method of claim 30, wherein the interposer substratecomprises a direct bonded copper (DBC) substrate so that the bottommetal layer comprises copper.
 33. The method of claim 31, wherein thetop copper layer is a patterned layer.
 34. The method of claim 30,wherein the laminate transformer supports a root mean square (RMS)breakdown voltage of at least 1 kV.
 35. The method of claim 30, whereinthe dielectric layer comprises a ceramic layer which provides a thermalconductivity at 20° C. of at least 20 W/m·K.
 36. The method of claim 30,wherein the circuitry for the first IC die or for the second IC diefurther comprises a DC/DC converter.
 37. A method for forming a devicepackage, comprising: providing an interposer substrate comprising a topcopper layer and a bottom metal layer with a dielectric layer positionedbetween the top copper layer and the bottom metal layer, and a leadframeincluding a plurality of leads or lead terminals; placing the interposersubstrate inside leads or lead terminals; dispensing an adhesive onto atleast the top copper layer; placing a laminate transformer, a first ICdie, and a second IC die, onto the adhesive; wirebonding respective onesof the first bond pads of the first IC die to first pads on the laminatetransformer and to a first group of the leads or the lead terminals, andrespective ones of the second bond pads of the second IC die to secondpads on the laminate transformer and to a second group of the leads orthe lead terminals, and forming a mold material over the laminatetransformer, the first IC die, and the second IC die, wherein the bottommetal layer is exposed from the ISO device package at least under thelaminate transformer.